Reduced Device Count Asymmetrical Multilevel Inverter Topology Using Different PWM Techniques Shubham Kumar Gupta Deparment of Electrical Engineering MITS Gwalior

Reduced Device Count Asymmetrical Multilevel
Inverter Topology Using Different PWM Techniques

Shubham Kumar Gupta
Deparment of Electrical Engineering
MITS Gwalior, India
[email protected]

Praveen Bansal
Department of Electrical Engineering
MITS Gwalior, India
[email protected]

Abstract– This paper presents a new topology in a
multilevel inverter (MLI) field with reduce device count and
less number of dc voltage source with different PWM
technique. This Proposed topology offers high power capability
associated with less commutation losses, less total harmonic
distortion (THD). For a specific number of levels in output,
proposed topology required less switching components and DC
voltage sources in comparison of Conventional topologies. This
topology used asymmetric voltage sources is in nature, that
required three asymmetric voltage sources and eight switching
devices for producing 15-Level single phase output voltage.
This topology is simple and optimal, which can be easily
extended for higher level in output voltage of multilevel
inverter. This paper presents the comparison of total harmonic
distortion, with different pulse width modulation technique,
with different modulation index, and the simulation result of
proposed topology for single phase 15-level multilevel inverter,
which are carried out by using MATLAB/Simulink R2013a
software version.
Keywords— Multilevel Inverter (MLI), Pulse Width
Modulation (PWM), Total Harmonic Distortion (THD)
I. INTRODUCTION
Multilevel inverter (MLI) is an extended form of an
inverter, which appears in power electronics systems in
1975, because of the requirement of the good quality power,
with better system efficiency 1. Multilevel inverters
becomes more popular over the years in high power medium
voltage application because of its capability of handling the
high power with less harmonic distortion (THD), reduced
switching losses and good power quality. As the number of
levels in output voltage waveform increases, harmonics in
the output voltage waveform decreases. In comparison with
two level inverter, multilevel inverter has several advantages
like lower commutation losses that’s why efficiency is
improved, less dv/dt stress across the switch, lower
harmonic contents, lower electromagnetic interference
(EMI), and reduced filter size 234. In multilevel
inverter (MLI) requirement of power electronics switching
components is more, which makes configuration complex
and costly 5, can be considered as a disadvantage of MLI.
Multilevel inverter is used to generate a multiple step
output waveform, to achieve smoother and less distorted DC
to AC power conversion at desired AC output voltage 6.
The general concept of multilevel inverter is, utilizing a
more number of semiconductor switches to perform the
power conversion in small voltage steps. There are mainly
three types of conventional multilevel inverter, Diode
clamped multilevel inverter (DCMLI) 7, Flying capacitor
multilevel inverter (FCMLI) 2, and cascaded H-bridge
(CHB) multilevel inerter 8. In DCMLI topology, as the
number of levels in voltage increased, more number of
clamping diodes required. In FCMLI topology, as the
number of levels in voltage increased, more number of
flying capacitor required. CHB multilevel inverter topology
is the simplest topology among the all conventional
topologies. In CHB multilevel inverter topology, clamping
diodes and flying capacitors are not required, but as the
number of levels in voltage increased, more number of DC
voltage sources required.
Generally, CHB multilevel inverters can be
classified in two types: Symmetric and Asymmetric
multilevel inverters. When the value of DC voltage sources
in H-bridges are equal, is called Symmetric multilevel
inverters. When the value of DC voltage sources in H-
bridges are unequal, is called Asymmetric multilevel
inverter. Asymmetrical topologies required less switching
devices and voltage sources as compared to symmetrical
topologies for same levels in output voltage. This paper
proposed a topology for Asymmetrical multilevel inverter,
which required less number of switching devices in
comparison with conventional topologies 4. For 15-Level
MLI total device count required in proposed topology is
compared with conventional topologies, shown in Table III.
This paper used different pulse width modulation techniques
to analyze total harmonic distortion in the output voltage
waveform.

II. PROPOSED TOPOLOGY
This paper proposed a topology based on
asymmetrical multilevel inerter, shown in Fig. 1, which
required N unequal voltage sources (V1, V2, V3….. VN) and
(2N+2) unidirectional switches (S1, S2, S3, S4….. S(2N+2) ),
for (2N-1) levels in output voltage of proposed multilevel
inverter. Generally, the proposed topology produces
maximum voltage (Vn + Vn-1). The proposed topology starts
with 7 level, for which two unequal voltage sources and six
unidirectional switches, consists of IGBT with an
antiparallel diode, required. For generating all positive and
negative levels, magnitude of voltage sources (V1:V2)
should be in the ratio of (1:2).
To generate 15-Level MLI, proposed topology
required three unequal voltage sources and eight
unidirectional switches, shown in Fig. 2, it is clear that
switching combination of (S1, S2), (S3, S4), (S5, S6), and
(S7, S8) should not be turned ‘ON’, simultaneously, to avoid
short circuit across the voltages. To generate all the positive
and negative levels in the output voltage, magnitude of the
voltage sources (V1:V2:V3) should be in the ratio of (1:2:5).
For different levels of 15-Level MLI, different switching

combinations are shown in Table I, in which, state 1 to state
7 present positive levels, state 8 present Zero level and state
9 to state 15 present negative levels in the output voltage
waveform of proposed MLI. State condition “1” and “0”
shows the corresponding switch is turn ‘ON’ or turn ‘OFF’,
respectively.
In this paper for 15-Level MLI, V1=50V,
V2=100V, V3=250V, and Load R= 10? is used, and ±350V,
±300V, ±250V, ±200V, ±150V, ±100V, ±50V, and 0V, are
the 15 levels in output voltage waveform generated, shown
in Fig. 9.
Proposed topology required ten unidirectional
switches and four unequal voltage sources to generate 31-
Level MLI, which can be obtain by adding two switches and
one voltage source in 15-Level MLI. Similarly, by
connecting more switches and more voltage sources, more
levels in output voltage of proposed MLI can be obtained.
TABLE I. SWITCHING SCHEME FOR PROPOSED 15-LEVEL MLI
STATES SWITCHING SCHEME OUTPUT
VOLTAGE
S1 S2 S3 S4 S5 S6 S7 S8
1 1 0 0 1 1 0 1 0 V3 + V2
2 1 0 0 1 0 1 1 0 V3 + V2 –=V1
3 0 1 0 1 1 0 1 0 V3
4 0 1 0 1 0 1 1 0 V3 –=V1
5 1 0 0 1 1 0 0 1 V2 + V1
6 1 0 0 1 0 1 0 1 V2
7 0 1 0 1 1 0 0 1 V1
8 0 1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 0 0
9 1 0 1 0 0 1 1 0 -V1
10 0 1 1 0 1 0 1 0 -V2
11 0 1 1 0 0 1 1 0 -(V2 + V1)
12 1 0 1 0 1 0 0 1 -(V3 –=V1)
13 1 0 1 0 0 1 0 1 -V3
14 0 1 1 0 1 0 0 1 -(V3 + V2 –=V1)
15 0 1 1 0 0 1 0 1 -(V3 + V2)

Fig. 1. General Structure of Proposed Topology

Fig. 2. Proposed Model of 15-Level Asymmetrical MLI
III. OPERATING MODES OF PROPOSED TOPOLOGY

Fig (a) + (V3 + V2) Fig (b) + (V3 + V2 – V1)
(Level +7) (Level +6)

Fig (c) + (V3) Fig (d) + (V3 – V1)
(Level +5) (Level +4) LOAD
V1V2
S1
S2
S3
S4
S5
S6Vo
Vn,
EVEN
Vn,
ODD LOAD
V1V2 V3
S1
S2
S3
S4
S5
S6
S7
S8
Vo LOAD
Vo
V1V2 V3
S1
S2
S3
S4
S5
S6
S7
S8 LOAD
Vo
V1V2 V3
S1
S2
S3
S4
S5
S6
S7
S8 LOAD
Vo
V1V2 V3
S1
S2
S3
S4
S5
S6
S7
S8 LOAD
Vo
V1V2 V3
S1
S2
S3
S4
S5
S6
S7
S8

Fig (e) + (V2 + V1) Fig (f) + (V2)
(Level +3) (Level +2)

Fig (g) + (V1) Fig (h) (0)
(Level +1) (Level 0)

Fig (i) – (V1) Fig (j) – (V2)
(Level -1) (Level -2)

Fig (k) – (V2 + V1) Fig (l) – (V3 – V1)
(Level -3) (Level -4)

Fig (m) – (V3) Fig (n) – (V3 + V2 – V1)
(Level -5) (Level -6)

Fig (o) – (V3 + V2)
(Level -7)
Fig. 3. Fig (a-o) are the different Operating Modes of Proposed Topology for 15-Level MLI.
IV. MULTI CARRIER PWM TECHNIQUES
The main purpose of modulation techniques is to
produce a train of switching pulses, which is responsible for
generating sinusoidal waveform at output voltage in
multilevel inverter (MLI). By proper use of these techniques
THD in the output can be reduced. In modulation techniques
Reference signal is compared with Carrier signal 9. For N-
level inverter (N-1) carrier waves are required. The most
popular modulation technique used is, Multi-Carrier based
Sinusoidal Pulse Width Modulation (MCSPWM) 10. In
this technique reference signal is sine wave of frequency 50
Hz and carrier signal is a triangular or inverted sine wave of
higher frequency than reference signal frequency. At each
and every point carrier signal is compared with the reference
signal, when the reference signal is greater than carrier
signal, switching pulse shows ‘1’ otherwise ‘0’. Addition of
the results of comparison between reference signal and
carrier signal produces the switching pulse which generates
levels in output voltage with different modulation index.
Modulation Index (Ma) is the ration of peak magnitudes of
the modulating waveform and the carrier waveform.
In this paper, PDPWM, PODPWM, and APODPWM
ISCPWM, and VFISCPWM techniques are used for 15-
Level MLI, shown in Fig. 4, Fig. 5, Fig. 6, Fig. 7, and Fig. 8
respectively.

? Phase Disposition Pulse Width Modulation
(PDPWM) Technique :–
In PDPWM technique, each and every
carrier waveforms are in same phase with same
amplitude and frequency.

Fig. 4. Carrier Arrangement for PDPWM techniques. LOAD
Vo
V1V2 V3
S1
S2
S3
S4
S5
S6
S7
S8 LOAD
Vo
V1V2 V3
S1
S2
S3
S4
S5
S6
S7
S8 LOAD
Vo
V1V2 V3
S1
S2
S3
S4
S5
S6
S7
S8 LOAD
Vo
V1V2 V3
S1
S2
S3
S4
S5
S6
S7
S8 LOAD
Vo
V1V2 V3
S1
S2
S3
S4
S5
S6
S7
S8 LOAD
Vo
V1V2 V3
S1
S2
S3
S4
S5
S6
S7
S8 LOAD
Vo
V1V2 V3
S1
S2
S3
S4
S5
S6
S7
S8 LOAD
Vo
V1V2 V3
S1
S2
S3
S4
S5
S6
S7
S8 LOAD
Vo
V1V2 V3
S1
S2
S3
S4
S5
S6
S7
S8
LOAD
Vo
V1V2 V3
S1
S2
S3
S4
S5
S6
S7
S8 LOAD
Vo
V1V2 V3
S1
S2
S3
S4
S5
S6
S7
S8

? Phase Opposition Disposition Pulse Width
Modulation (PODPWM) Technique :–
In PODPWM technique, all carrier
waveforms above zero reference line are in same
phase with same amplitude and frequency, but
carrier waveforms below zero reference line are
180o out of phase to above zero reference line
carrier waveforms with same amplitude and
frequency.

Fig. 5. Carrier Arrangement for PODPWM techniques.
? Alternate Phase Opposition Disposition Pulse
Width Modulation (APODPWM) Technique :–
In APODPWM technique, all carrier
waveforms has same amplitude and frequency, but
all the carrier waveforms are 180o out of phase
with by its neighboring carrier waveforms.

Fig. 6. Carrier Arrangement for APODPWM techniques.
? Inverted Sine Carrier Pulse Width Modulation
(ISCPWM) Technique :–
In ISCPWM technique, reference signal
is sinusoidal waveform and carrier signals are
inverted sinusoidal waveforms. Frequency of
carrier signals are higher than reference signal,
which presents high fundamental output voltage
11.

Fig. 7. Carrier Arrangement for ISCPWM techniques.
? Variable Frequency Inverted Sine Carrier Pulse
Width Modulation (VFISCPWM) Techniques :–
In VFISCPWM technique, reference
signal is sinusoidal waveform and carrier signals
are inverted sinusoidal waveforms with variable
frequencies. In this technique, frequencies of
carrier signals are higher than reference signal.
This technique provides an enhanced fundamental
voltage and lower Total Harmonic Distortion
(THD) 12.

Fig. 8. Carrier Arrangement for VFISCPWM techniques.
V. SIMULATION RESULTS
The proposed topology for 15-Level asymmetric
multilevel inverter, simulated in MATLAB. Table III shows
the comparison of device count between proposed topology
and conventional topologies for 15-Level MLI. Table I
shows the switching schemes for 15-Level MLI. Table II
shows comparison between Total Harmonic Distortion
(THD) for different modulation technique at different
modulation index. The Simulation parameters for 15-Level
MLI are as following Resistance R=10? and DC Voltage
sources are V1=50V, V2=100V, and V3=250V. Output
Voltage Waveform of 15-Level MLI shown in Fig. 9. This
paper used five modulation techniques, PDPWM,
PODPWM, APODPWM, ISCPWM, and VFISCPWM with
different Modulation Index, at carrier signal frequency
2000Hz. Total Harmonic Distortion is carried out by using
FFT analysis in MATLAB/Simulink R2013b, shown in
Fig. 10, Fig. 11, Fig. 12, Fig. 13, and Fig. 14, respectively.

Fig. 9. Output Voltage Waveform of 15-Level Proposed Asymmetrical Multilevel Inverter (ASMLI)

Fig. 10. %THD of 15-Level ASMLI with PDPWM technique (Ma=1 and Mf=40)

Fig. 11. %THD of 15-Level ASMLI with PODPWM technique (Ma=1 and Mf=40)

Fig. 12. %THD of 15-Level ASMLI with APODPWM technique (Ma=1 and Mf=40)

Fig. 13. %THD of 15-Level ASMLI with ISPWM technique (Ma=1 and Mf=40)

Fig. 14. %THD of 15-Level ASMLI with VFISCPWM technique (Ma=1 and Mf=40)
TABLE II. COMPARISON OF %THD FOR DIFFERENT MODULATION TECHNIQUES WITH DIFFERENT MODULATION INDEX (MA)
Level Modulation
Index
Modulation Techniques
PD POD APOD ISC VFISC

7
Level
1 18.23 18.18 18.39 19.67 19.97
0.95 20.59 20.60 20.23 21.43 21.81
0.90 22.40 22.11 21.98 22.77 22.65

15
Level
1 7.85 8.62 7.65 8.41 7.96
0.95 8.56 8.53 8.89 9.12 8.68
0.90 8.80 8.26 8.67 9.46 8.84

TABLE III. COMPARISON OF COMPONENTS USED FOR 15-LEVEL MLI BETWEEN PROPOSED TOPOLOGY AND CONVENTINAL TOPOLOGIES
MLI
Component
Diode
Clamped
Flying
Capacitor
Cascaded
H-Bridge
Proposed
Topology
Switching
Devices 28 28 28 8
Clamping
Diode 182 0 0 0
DC Split
Capacitor 14 14 0 0
Clamping
Capacitors 0 91 0 0
DC
Sources 1 1 7 3

VI. CONCLUSION
This paper presents a new asymmetrical multilevel inverter
(ASMLI) topology, which has greater performance than
conventional topologies. The proposed ASMLI topology
reduces total harmonic distortion (THD), shown in table. II,
and modify the output voltage waveform. From table. III,
the proposed topology required less switching components
in comparison of conventional (DCMLI, FCMLI, and
CHBMLI) topologies, so that the overall cost of switching
components required, is reduced and efficiency improved.
For 15-Level MLI, THD is 7.65% by using alternate phase
opposition disposition pulse width modulation
(APODPWM) technique with modulation index (Ma=1).
The introduced topology was simulated and Harmonics
analysis carried out by using MATLAB/Simulink R2013a
version software.

VII. ACKNOWLWDGEMENT
The author gratefully acknowledges the guidance and
support of Electrical Engineering Department, MITS
Gwalior for Carrying out this work.
VIII. REFERENCES
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